This is Set I of our three Computer Organization and Architecture (COA) MCQ sets. It covers register transfer language, the common bus system built from multiplexers or three-state buffers, and how data moves between memory and registers through AR and DR. The notation follows Morris Mano's Computer System Architecture, which most Indian university syllabi use.
We rewrote this set in October 2026. The old version had repeated questions, unclear wording and a few wrong answers. Every question below now stands on its own, the numeric ones have been checked, and each answer comes with a short reason.
How to use this set: pick an option for each question. You will see straight away whether it is right, with a short note on why. There are 15 questions.
What this set covers
- Register transfer language and its notation
- Control functions such as
P: R2 ← R1 - Common bus built from multiplexers
- Three-state buffers and bus decoders
- Memory read and write using AR and DR
- Sizing registers and buses from memory size
Computer Organization and Architecture MCQs with answers and explanations
Q1. In register transfer language, what does the statement R2 ← R1 mean?
a) The contents of R2 are copied into R1
b) R1 and R2 swap their contents
c) The contents of R1 are copied into R2
d) R1 is cleared and R2 is loaded with zero
Q2. What does the statement P: R2 ← R1 describe?
a) P is loaded with the contents of R1 and R2
b) R2 is copied into R1 when P is 0
c) R1 is copied into R2 on every clock pulse
d) R1 is copied into R2 only when the control function P is 1
Q3. In RTL, what does the notation R1(0-7) or R1(L) refer to?
a) A memory word at address R1
b) Eight separate registers named R1
c) The register R1 shifted left by seven places
d) A group of bits inside register R1, such as its low byte
Q4. What does a comma between two micro-operations mean, as in T: R2 ← R1, R1 ← R2?
a) The two operations run one after the other in two clock pulses
b) The operations are alternatives and only one is chosen
c) Both operations happen in the same clock pulse
d) The second operation is skipped if the first fails
Q5. A common bus connects 8 registers, and multiplexers are used to choose which register drives the bus. How many select lines does each multiplexer need?
a) 8
b) 4
c) 3
d) 2
Q6. A bus system for 4 registers of 16 bits each is built with multiplexers. How many multiplexers are needed, and of what size?
a) 4 multiplexers of size 4 x 1
b) 16 multiplexers of size 4 x 1
c) 16 multiplexers of size 16 x 1
d) 4 multiplexers of size 16 x 1
Q7. What are the three output states of a three-state buffer?
a) Logic 0, logic 1 and unknown
b) Logic 0, high impedance and ground
c) Logic 1, high impedance and short circuit
d) Logic 0, logic 1 and high impedance
Q8. Why are three-state buffers useful for building a common bus?
a) They double the speed of the bus
b) They let many outputs connect to one bus line, with only the enabled one driving it
c) They store data between clock pulses
d) They add two registers before placing the result on the bus
Q9. A bus with three-state buffers connects 4 registers. A decoder selects which register's buffers are enabled. What size of decoder is needed?
a) 2 x 4
b) 3 x 8
c) 4 x 16
d) 1 x 2
Q10. How many three-state buffers are needed to connect 4 registers of 8 bits each to a common 8-bit bus?
a) 8
b) 12
c) 32
d) 64
Q11. What does the RTL statement Read: DR ← M[AR] do?
a) Reads the memory word whose address is in AR and places it in DR
b) Reads the word at address DR and puts it in AR
c) Writes DR into memory at the address held in AR
d) Copies AR into DR
Q12. Which RTL statement describes a memory write using the address register AR and a register R1?
a) M[AR] ← R1
b) R1 ← M[AR]
c) AR ← M[R1]
d) M[R1] ← AR
Q13. A memory has 4096 words of 16 bits each. How many bits must the address register AR have?
a) 16
b) 4096
c) 10
d) 12
Q14. A memory unit has 1M (2^20) words of 32 bits each. Which pair gives the number of address lines and data lines?
a) 10 address lines and 32 data lines
b) 20 address lines and 32 data lines
c) 32 address lines and 20 data lines
d) 20 address lines and 20 data lines
Q15. In a bus system, registers have a LD (load) input. What happens when LD of a register is 1 at the clock edge?
a) The register increments by one
b) The register is cleared to zero
c) The register takes in the data currently on the bus
d) The register places its contents on the bus
Quick revision notes
- In RTL the destination is on the left of the arrow. A transfer copies data and leaves the source unchanged.
- A control function written before a colon (
P:) decides when the transfer happens. A comma means two operations in the same clock pulse. - Multiplexer bus for k registers of n bits: n multiplexers, each k x 1, with log2(k) select lines.
- Three-state bus: one buffer per bit per register, and a decoder (2 x 4 for 4 registers) to enable one register at a time.
- Memory read is
DR ← M[AR]and write isM[AR] ← DR. AR width comes from the number of words, DR width from the word size.
Frequently asked questions
Which textbook do these COA questions follow?
The notation and examples follow Morris Mano's Computer System Architecture, chapters on register transfer and micro-operations. Most Indian university COA syllabi use the same notation.
Is a multiplexer bus or a three-state bus used in real processors?
Both ideas appear. Multiplexers are common inside chips because they are easy to design and test, while three-state buffers are typical for shared external buses where many devices connect to the same wires.
How do I quickly find the address bus width for a memory size?
Write the number of words as a power of 2 and take the exponent. For example 64K words is 2^16, so 16 address lines. The bits per word do not affect the address width.
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