This set moves to the memory and performance side of Computer Organization: cache mapping numericals, average access time, write policies, pipeline speedup and hazards, and the main I/O transfer methods. It suits GATE aspirants, university exam preparation and technical interviews, and every numerical shows its working.
How to practise: read each question and tap the option you think is correct. You will see right away whether you got it, along with a short explanation, and your score is tracked at the bottom of the screen. This set has 18 questions.
Topics covered in this set
- Memory hierarchy and write policies
- Direct, associative and set-associative mapping
- Hit ratio and average access time
- Pipeline speedup and stage timing
- Structural, data and control hazards
- Programmed I/O, interrupts and DMA
Computer organization MCQs with answers and explanations
Q1. In the memory hierarchy, as we move from CPU registers towards magnetic disk, which trend holds?
a) Access time decreases
b) Cost per bit increases
c) Capacity increases while cost per bit decreases
d) Capacity decreases while access time increases
Q2. Which statement about the write-back cache policy is correct?
a) Main memory is updated only when a modified (dirty) block is evicted from the cache
b) Every write updates both the cache and main memory at the same time
c) It does not need a dirty bit
d) It keeps main memory always consistent with the cache
Q3. A pipeline has a single memory port, and in one cycle an instruction fetch and a data load both need memory. This conflict is a:
a) Data hazard
b) Control hazard
c) WAR hazard
d) Structural hazard
Q4. What dependency exists between the two instructions below?
ADD R1, R2, R3 ; R1 <- R2 + R3 SUB R4, R1, R5 ; R4 <- R1 - R5
a) Read after write (RAW) on R1
b) Write after read (WAR) on R1
c) Write after write (WAW) on R4
d) Control dependency
Q5. Which statement best describes programmed I/O?
a) The device transfers data directly to memory without CPU involvement
b) The CPU repeatedly checks the device status flag and transfers each word itself
c) The device interrupts the CPU only when data is ready
d) A separate I/O processor executes channel programs
Q6. What is the defining feature of a vectored interrupt?
a) The CPU polls each device to find the source
b) All devices share one fixed service routine address and software identifies the source
c) Interrupts stay disabled until the current program ends
d) The interrupting device supplies an identifier or address that leads directly to its service routine
Q7. In cycle-stealing mode of DMA, the DMA controller:
a) Lets the CPU copy each word from the device buffer to memory
b) Holds the bus until the entire block has been transferred
c) Takes over the bus for one word at a time, briefly delaying the CPU's memory access
d) Executes instructions fetched from main memory
Q8. A direct-mapped cache has 128 lines. Main memory block number 1000 is placed in which cache line?
a) 8
b) 104
c) 125
d) 72
Q9. A 32-bit byte-addressable machine has a 64 KB direct-mapped cache with 32-byte blocks. How many bits are used for tag, line index and block offset respectively?
a) 16, 11, 5
b) 15, 12, 5
c) 16, 12, 4
d) 21, 6, 5
Q10. The same 64 KB cache with 32-byte blocks (32-bit byte addresses) is made 4-way set associative. How many tag bits and set-index bits are needed?
a) 16 and 11
b) 17 and 10
c) 20 and 7
d) 18 and 9
Q11. If the same 64 KB cache with 32-byte blocks (32-bit byte addresses) is fully associative, how many bits are in each tag?
a) 16
b) 21
c) 27
d) 32
Q12. A cache has an access time of 10 ns and main memory 100 ns, with a hit ratio of 0.9. Main memory is accessed only after a cache miss is detected (hierarchical access). What is the average memory access time?
a) 19 ns
b) 20 ns
c) 10.9 ns
d) 28 ns
Q13. A system has cache access time 5 ns and main memory access time 50 ns, with cache and memory accessed simultaneously (Tavg = h x Tc + (1 - h) x Tm). What hit ratio gives an average access time of 9.5 ns?
a) 0.81
b) 0.85
c) 0.95
d) 0.90
Q14. A fully associative cache holds 3 blocks and uses LRU replacement. Starting empty, how many misses occur for the block reference sequence 1, 2, 3, 1, 4, 2, 5, 1?
a) 5
b) 6
c) 7
d) 8
Q15. A 5-stage pipeline with equal stage delays and no stalls executes 100 instructions. What is the speedup over an equivalent non-pipelined processor (ignoring latch overhead)?
a) 5.00
b) 4.81
c) 4.95
d) 4.50
Q16. A 4-stage pipeline has stage delays of 20 ns, 30 ns, 40 ns and 25 ns, and each inter-stage latch adds 5 ns. How long does it take to execute 1000 instructions with no stalls?
a) 45.135 µs
b) 40.12 µs
c) 115 µs
d) 45.0 µs
Q17. In the classic 5-stage RISC pipeline (IF, ID, EX, MEM, WB) with full forwarding, how many stall cycles are needed when LW R1, 0(R2) is immediately followed by ADD R3, R1, R4?
a) 0
b) 1
c) 2
d) 3
Q18. In a pipelined processor with ideal CPI 1, 20% of instructions are branches and each branch causes 2 stall cycles. What is the effective CPI?
a) 1.2
b) 1.6
c) 1.4
d) 2.2
Quick revision notes
- Direct mapping: line = block mod lines; address = tag | index | offset.
- Set-associative: sets = lines / k; index bits = log2(sets); fully associative has no index field.
- Hierarchical Tavg = h*Tc + (1-h)*(Tc+Tm); simultaneous Tavg = h*Tc + (1-h)*Tm.
- Write-through keeps memory consistent; write-back uses a dirty bit and writes on eviction.
- Pipeline time = (k + n - 1) x cycle; speedup = nk / (k + n - 1); cycle = slowest stage + latch delay.
- Hazards: structural (resource clash), data (RAW/WAR/WAW), control (branches); load-use needs 1 stall even with forwarding.
- Effective CPI = 1 + sum of (stall frequency x stall cycles).
- Programmed I/O polls; interrupt-driven I/O avoids busy-waiting; DMA moves blocks via cycle stealing or burst mode.
Frequently asked questions
How do I find tag, index and offset bits for a cache?
Offset bits = log2(block size). Index bits = log2(number of lines) for direct mapping or log2(number of sets) for set-associative mapping. Tag bits are whatever remains of the physical address.
Why is the actual pipeline speedup less than the number of stages?
Filling the pipeline takes k - 1 extra cycles, stages are rarely perfectly balanced, latches add delay, and hazards cause stalls. The ideal speedup of k is reached only for a very long stream of instructions with no stalls.
What is the difference between interrupt-driven I/O and DMA?
With interrupt-driven I/O the CPU is interrupted for every word or small unit and transfers it itself. With DMA the CPU only sets up the transfer; the DMA controller moves the whole block between device and memory and interrupts the CPU once at the end.
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